1. Field of the Invention
The present invention relates to a multiplier, more particularly, it relates to a parallel multiplier and specifically to a configuration of circuit portions which perform its addition.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a general configuration of a prior art parallel multipler of 8 bits.times.8 bits.
In the figure, numeral 1 denotes an AND circuit which propagates only a result of partial product to the following step, 2 is a half adder for adding a sum and partial product in the preceding step, 3 is a full adder for adding the sum, carry and partial product in the preceding step, numeral 4 indicates a group of adders which add the sum and carry of each position, and FA represents the full adder and HA represents the half adder. The AND circuit 1, half adder 2, full adder 3, full adder FA and half adder HA respectively constitutes logic cell, between which sum signals SS of the sum and carry signals CS of the carry are propagated respectively through signal lines 5 (full lines) and 6 (broken lines).
Referring now to the operation, in FIG. 1, when one lateral line is assumed as one step, first, in the AND circuit in the first step, partial products (X.sub.0 Y.sub.0 to X.sub.7 Y.sub.0) of 0 bit (Y.sub.0) of a multiplier Y and 0 to 7 bits (X.sub.0 to X.sub.7) of a multiplicand X are calculated, thereby the AND circuit 1 outputs its result as the sum signal SS to the half adder 2 of the same position in the second step through the signal line 5. In the next second step, the sum signal SS and partial products (X.sub.0 Y.sub.1 to X.sub.7 Y.sub.1) are added and its result is outputted to the full adder in the third step as the sum signal SS and carry signal CS together with the sum signal SS of the partial product (X.sub.7 Y.sub.1). Then, in the third step, the sum signal 5, carry signal 6 and each partial product (X.sub.0 Y.sub.2 to X.sub.6 Y.sub.2) are added and in the same way as the second step, the sum signal 5 and carry signal 6 are outputted to the next step. Same additions are repeated till the 8th step, and in a circuit group 4 in the last 9th step, the sum signal 5 and carry signal 6 in each position are added to obtain a final sum (product).
Since the prior art multiplier is constructed as described heretofore, it was disadvantageous in that, an operation speed is delayed because the partial products of each position must be added successively, and as the number of bits increases the adding step increases similarly.